The specification only defines the upper layers of the RRPGE system, the parts necessary to make it appearing consistent for the user (the application developer).
Although I am not a hardware engineer, I do have some insight to these matters. The specifications did not came from thin-air, I actually sketched up some internal concepts of the system, such as how the CPU's pipeline may be composed. To put it short, these exist, I just had no time yet to add them to the appropriate supplementary section of the RRPGE specification.
Of course later I will do. It would be interesting how the system actually fared in hardware, which probably may be explored later with the help of VHDL and an FPGA. Of course it is a quite large job to get there, something which certainly won't be done by me.